FPGA-based hybrid accumulator architecture for digital chirp synthesis
Sana Salous, C. K. ONG · International Journal of Electronics · 1996
The double accumulator architecture can be employed to generate chirp signals with the required linearity for both radar and sounder applications. However, all reported chirp generators use identical architecture for both accumulators. In this paper, a FPGA-based hybrid accumulator architecture with a dual clock suitable for HF radar and sounder applications is proposed. This design is shown to combine speed and flexibility.