Highly-Associative Caches for Low-Power Processors
Michael Zhang, Krste Asanović · 2000
Introduction Since caches consume a significant fraction of total processor energy, e.g., 43% for StrongARM-1 [8], many studies have investigated energy-efficient cache designs [1, 5, 12, 13, 14, 15, 18]. However, none of these design studies have considered using content-addressable-memory (CAM) tags in highly-associative caches. This is particularly surprising given that the leading commercial lowpower processors over the last decade have all employed CAM-tag caches. For example, the ARM3 with 4 KBytes of 64-way set-associative CAM-tag cache was released in 1989 [9] and the new Intel XScale processor employs 64way set-associative CAM tags. Publications which describe processors with CAM-tag caches [8, 9, 11, 16] include some discussion of the reasons for choosing CAM tags but do not include detailed quantitative arguments in favor of these designs. In this paper, we restate the advantages of CAM-tag caches based on a new cache energy model extracted from circuit designs for ag