DS-CDMA wired bus with simple interconnection topology for parallel processing system LSIs
R. Yoshimura, Tan Boon Keat, T. Ogawa, Shingo Hatanaka, Toshimasa Matsuoka, Kenji Taniguchi · 2002
A new bus architecture is suitable for a parallel processing system without complexity of interconnection, and also drastically reduces the I/O pin count, which is highly desirable for future gigascale integrated systems.The architecture is based on the direct sequence code division multiple access (DS-CDMA) technique [1].