An ASIP encoder for Quasi-Cyclic LDPC codes
Xiaojun Zhang, Yinghong Tian, Jianming Cui, Yanni Xu, Zongsheng Lai · 2009
This paper proposes a LDPC (Low Density Parity Check Codes) encoder architecture for DMB-TH based on ASIP (Application Specific Instruction Set Processor). The encoding algorithm is first analyzed and optimized for the ASIP encode, And then the special instruction sets are extracted according to the optimized algorithm. The ASIP architecture uses main processor and coprocessor to get high throughput. This ASIP encoder can support three different code rates (0.4, 0.6 and 0.8) just by different programs and thus is more flexible than other ASIC implementations. Based on XC2V6000, at the max frequency of 117 MHz, the max throughput of the encoder can deliver 187 Mbps, 206 Mbps and 232 Mbps for 0.4, 0.6 and 0.8 code rates, respectively.