Design and Implementation of Buffer Loan Algorithm for BiNoC Router
Deepa S Dev · International Journal of Engineering Trends and Technology · 2014
Novel BiNoC router architecture is presented that supports dynamic self-reconfiguration of channel direction and buffer reconfiguration. In conventional BiNoC architecture to accommodate heavy traffic, large buffer is needed. But the proposed router (BiNoC router with reconfigurable buffer) can support heavy traffic without the need of large buffer. In this case power dissipation is less and performance is better than conventional BiNoC router. The designing has been done using the hardware description language VHDL in XILINX ISE tool. Its FPGA implementation is done using Virtex-5 board.