Two 156 Mbit/sec CMOS Chips For Sdh/Sonet 2.5 Gbit/sec European Transmission Systems
Yi‐Kai Lo, L. Mai, T.C. Poon, Aryeong Lee, L.S. Juang, H.Y. Park, M. Luong, J. Aubertin, N. Dekerckheer, J. Gude, Dankwart Koehler, P. Vergauwen · 1992
This paper will describe two 30K-gate chips which have been designed and fabricated to transmit and receive CEFT4 and STM-1 signals at 140 Mbiti sec and 156 Mbitisec data rate operations for SDHiSONET 2.5 Gbitisec transmission systems. A mixed full custom and standard cell design technique has been demonstrated to be very effective in providing short design intervals and attractive costs for high speed, low power systems.