A study on hybrid switch architecture using hierarchical memory system
Hiroshi Ishikawa, Yasuharu Kosuge, Noriharu Miyaho · Electronics and Communications in Japan (Part I Communications) · 1986
Abstract On the premise that flexibility in communication is a primary objective for future digital networks providing various services, it is highly desirable to integrate circuit switching (CS) and packet switching (PS) functions into a single switching node. This paper proposes a hybrid switching system where PS and CS switching functions are integrated by making use of a hierarchical memory system in which the CS and PS switching buffers and program buffers reside in the same memory area, and the high‐speed memory in the hierarchy can be accessed both by transmission lines and processors. The design concept which adopts a new architecture necessary to meet the above requirement and the evaluation of its call processing capacity using traffic simulation and theoretical analysis are described.