A true block pipelined programmable Reed-Solomon CODEC for high-speed/low-power applications
Hyung-Joon Kwon, Jae‐Shin Lee, Seung Hoon Lee, Bong Young Jeong · 2002
Proposes a Reed-Solomon CODEC architecture. The chip was fabricated using 0.35/spl mu/m technology. Since it was implemented as a programmable CODEC which,can correct up to 16 errors/32 erasures at once, it has versatility regardless of the number of correctable errors and the length of codeword for various applications. Suggested RS-CODEC has "true block pipelined architecture" in which frame latency is equal to the length of codeword leading to maximize throughput to achieve high-speed and low-power at the same time. The input data rate can amount to 100MByte per sec.