A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes
Paul Saunders, Anthony Fagan · 2006
We propose a novel, high speed, low memory fully programable FPGA decoder architecture to decode quasi-cyclic LDPC codes. By performing optimizations at the code construction, algorithmic and architecture levels we are able to achieve significant throughput and memory storage advantages over current FPGA decoder implementations. Our decoder employs the modified turbo decoding algorithm, to achieve a decoding throughput of 223 Mbps for a frame length of 3200 bits whilst only consuming 71 Kb of memory using a Xilinx Virtex-4 architecture.