Iddq fault model generation for BiCMOS and CMOS circuits
V. Panic, D. Milovanovic · 2002
In this paper, an approach for Iddq test generation for BiCMOS and CMOS VLSI circuits is presented. After a brief review of Iddq testing, basic ideas and general problems in Iddq testing of BiCMOS and CMOS VLSI are given. The application of this method is illustrated on three basic examples for BiCMOS and one for CMOS VLSI circuits. Circuits are simulated on PSpice, and results of these simulations are presented in an appropriate form. Finally, the possibilities for further research in Iddq testing for both BiCMOS and CMOS VLSI circuits are mentioned.