Built-In self-repair for divided word line memory
Shyue-Kung Lu, Chih-Hsien Hsu · 2002
In this paper, a novel block-repair fault-tolerant architecture based on the characteristics of divided word line (DWL) is proposed for high-capacity memories. We divide the memory cell array into blocks and redundancies are added at the block level. Our fault-tolerant architecture can improve the yield for memory fabrication significantly. According to experimental results, the hardware overheads are less than 0.732% and 0.48% for SRAMs and DRAMs, respectively, It also concludes that the block repair approach improves repair rate significantly.