Pedestrian detection implemented on a fixed-point parallel architecture
T.C. Wilson, Michael Glatz, Michael Hödlmoser · 2009
This paper describes the implementation of a real-time pedestrian detector on a single instruction, multiple data (SIMD), fixed-point digital signal processor (DSP). We reformulate the Histogram of Oriented Gradients algorithm for calculation with a relatively simple instruction set architecture (ISA) and partition the image for parallel processing. Results obtained using an ISA simulator indicate a maximum frame rate above 40 fps for 1 MPixel images, with a detection accuracy comparable to a double-precision floating-point reference implementation.