The Span Cache: Software Controlled Tag Checks and Cache Line Size
Emmett Witchel · 2001
The span cache is a hardware-software design for a new kind of energy-efficient microprocessor data cache which has two key features. The first is direct addressing which allows software to access cache data without the hardware performing a cache tag check. These tag-unchecked loads and stores save the energy of performing a tag check when the compiler can guarantee an access will be to the same line as an earlier access. The second key feature is software controlled line size. This lets the compiler specify how much data to fetch on a miss, allowing greater cache utilization and reducing memory bandwidth requirements. Two possible hardware implementations of software controlled line size are sketched and discussed.