Resource allocation in a high clock rate microprocessor
Michael Upton, Thomas Richard Huff, Trevor Mudge, Richard B. Brown · ACM SIGPLAN Notices · 1994
This paper discusses the design of a high clock rate (300MHz) processor. The architecture is described, and the goals for the design are explained. The performance of three processor models is evaluated using trace-driven simulation. A cost model is used to estimate the resources required to build processors with varying sizes of on-chip memories, in both single and dual issue models. Recommendations are then made to increase the effectiveness of each of the models.