Different experiments in test generation for XILINX FPGAs
M. Renovell, Y. Zorian · 2002
In this paper, we describe an experiment about structural testing of two XILINX FPGAs families. In our practical approach, the FPGA is divided into different arrays: an array of logic cells, an array of interconnect cells and an array of RAM cells. For each part, we use a specific fault model and we generate test configurations and test vectors for the considered models. In each case, for each array, we try to minimize as much as possible the number of test configurations because re-programming FPGAs is really time consuming.