Integrated Procedure Automating Test Chip Layout, Place and Route, and Test Plan Development for Efficient Parametric Device and Process Design
Ann Gabrys, Wendy Greig, Andrew J. West, Philipp Lindorfer, William D. French, Samrat Mondal, Devjyoti Patra, Kalyan Goswami, Shamik Sural, Timothy Crandle · IEEE Transactions on Semiconductor Manufacturing · 2009
This work describes a novel system for device development that automates and fully integrates the workflow from test chip construction, from placement and routing to electrical test program generation. In addition to accelerating test chip and test program development, this system facilitates parameterized data analysis, thereby providing a framework that finally allows the user to realize the full benefits of complex and elegant experimental device designs. By utilizing a centralized database and eliminating parameter re-entry, the automation provided by this integrated approach eliminates many of the sources for human error while maximizing reuse between technologies.