Fast fair arbiter design in packet switches
Feng Wang, Mounir Hamdi · 2005
All arbiters proposed in the literature suffer front one of the following problems: large time complexity and/or unfairness. The first generation arbiters for switches take into consideration the issue of fairness by using a rotating round robin priority list, but their arbitration time is proportional to the number of inputs which makes them unscalable for a given fixed amount of arbitration time. To reduce the time complexity, Chao, et al. (2001) proposed a tree arbiter structure which can perform the arbitration in a fast and efficient way, but this framework can not guarantee fairness to all the inputs. When it is fed by adversary traffic, some of the traffic may not get its fair share of the bandwidth. Motivated by solving these two problems, we propose a new algorithm which guarantees fairness and has O(logN) time. In addition, we explore the possibility that our solution of arbiter design can be embedded into the switch crossbar, thus reducing the cost as well as power consumption.