VLSI architectures for a high-speed tunable digital modulator/ demodulator/bandpass-filter chip set
Henry Samueli, T. Lin, Robert Hawley, S. Olafson · 2003
An all-digital multirate CMOS chip set architecture is presented for implementing tunable digital modulators, demodulators, and bandpass filters with a projected throughput rate of 200 Msamp/s in a 1.0- mu m CMOS process. The proposed three-chip set will accommodate center frequencies up to 90 MHz and selectable bandwidths from a few kHz up to tens of MHz. The first chip consists of a Hilbert transformer to implement a double-sideband to single-sideband conversion. The second chip consists of a quadrature oscillator and a complex multiplier to implement frequency translation, and the third chip consists of a multistage decimation/interpolation lowpass filter with selectable bandwidths. The authors discuss the architecture techniques used to achieve a 200-MHz throughput rate in a modest CMOS technology.>