200 mega pixel rate IDCT processor for HDTV applications
C.S. Kim, Su-Han Song, M.Y. Kim, Yunseok Han, SeoWon Kang, B.W. Lee · 1993 IEEE International Symposium on Circuits and Systems · 2002
A high-speed video rate 8 /spl times/ 8 inverse discrete cosine transform (IDCT) processor using a distributed arithmetic architecture is presented. 64-point one-dimensional IDCT processing units are simultaneously operated with 8 clock cycles. With these 64 fully parallel units and three-stage pipeline structure for each unit, the latency time of this proposed architecture is only 37 cycles. ROM banks containing IDCT coefficients are minimized to 12 by applying two pixel bits per clock. This VLSI is fabricated in 1.0-/spl mu/m double metal CMOS process with 120 mm/sup 2/ die area. It consumes approximately 3 watts at a 5 volt operating voltage and 50 MHz master clock frequency. Since critical path delay is given as 15.5 nsec, this proposed chip has enough speed for digital HDTV applications.>