Single chip implementation of real time RNS IIR digital filters
G.C. Cardarilli, R. Lojacono, Mário Sérgio Salerno, F. Sargeni · 2003
VLSI realization of single chip IIR digital filters is described. In order to improve speed performance, the arithmetic operations are implemented in parallel, on the basis of residue number system technique. The main feature of the realization is that the delay time related than 100 nsec, so that filters with more than 10 MHz clock rate cane be obtained. Even though an 8 bit wordlength is used for signals, the overall accuracy of the filter is far better than that of an 8 bit conventional realization, because of the favourable properties of the finite arithmetic which makes most inner operations free of arithmetic errors. The final layout has been realized with 1.5 micron CMOS standard cell technology.>