Experimental Demonstration of Concatenated LDPC and RS Codes by FPGAs Emulation
Takashi Mizuochi, Y. Konishi, Yoshikuni Miyata, T. Inoue, Kiyoshi Onohara, Soichiro Kametani, Takashi Sugihara, K. Kubo, Hideo Yoshida, Toshifumi Kobayashi, T. Ichikawa · IEEE Photonics Technology Letters · 2009
The concatenation of low-density parity-check and Reed-Solomon codes for forward error correction has been experimentally demonstrated for the first time in this letter. Using a 2-bit soft-decision large-scale integration and high-speed field-programmable gate arrays, a net coding gain of 9.0 dB was achieved with 20.5% redundancy with four iterative decoding for an input bit-error rate of 8.9 times 10-3at 31.3 Gb/s.