Design and FPGA implementation of image block encoders with 2D-DWT
G. Lakshminarayanan, B. Venkataramani, J.S. Kumar, Aamir Yousuf, Gokul Sriram · 2004
In this paper schemes for computation of 2D DWT of 32 /spl times/ 32 subimages using both lifting and DAA technique with Baugh-Wooley multiplier (BWM) is proposed and implemented on Xilinx XC2S150PQ208-5 FPGAs. The implementation results show that the lifting scheme with BWM requires about 20% less area but is 1.55 times faster than that using conventional 2s complement multiplier (C2M). For larger word sizes, the DAA with BWM is found to be 1.2 times faster than that using C2M. An overlap method for processing 128 /spl times/ 128 image using subimages of size 32 /spl times/ 32 is proposed and implemented. The 2D DWT of the image is also computed using a C program. The LL1 component of the image obtained using all the above schemes are found to be matching well with the original image. FPGA implementation of higher level 2D DWT is under progress.