A 1.8 V 36 mW DSP for the half-rate speech codec
Taketora Shiraishi, K. Kawamoto, K. Ishikawa, Hisayasu SATO, F. Asai, E. Teraoka, Toru Kengaku, Hiroyuki Takata, Takeshi Tokuda, Kazuya Nishida, Kazunori Saitoh · 2002
A low-power 16-bit DSP has been developed to realize a low bit-rate speech codec. A dual datapath architecture and low-power circuit design techniques are employed to reduce power consumption. The PDC half-rate speech codec is implemented in the DSP with 36 mW at 1.8 V.