High speed architectures for two-dimensional state-space recursive filtering
J.Y. Zhang, W.J.D. Steenaart · IEEE Transactions on Circuits and Systems · 1990
A description is given of 2-D state-space filter algorithms, and two VLSI architectures for high-speed applications are proposed. The advanced state update architecture trades increased throughput rate and a simple input-output scheme for increased hardware. The technique is based on block processing. The state update matrix is changed by recursive multiplications, and the advanced state vector can be calculated. This architecture is a two-dimensional systolic array. It can process one pixel during each multiplication/addition clock period with a regular line-by-line scanning method. To achieve very high speed, the global speedup architecture is utilized by exploiting the inherent spatial concurrency. This architecture consists of a number of column array processors. Based on the computational independence between the samples along the diagonal lines in a first-quadrant 2-D system, it works on multiple columns of images concurrently. The architecture is very modular and flexible. The throughput rate can be very high and is adjustable by changing the number of column processors. Different high-speed architectures for image processing are compared.>