A 125-mm/sup 2/ 1-Gb NAND flash memory with 10-MByte/s program speed
K. Imamiya, Hiroshi Nakamura, Toshihiko Himeno, T. Yarnamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Kiyoyuki Kawai, R. Shirota, N. Arai, Fumitaka ARAI, K. Hatakeyama, Hiroaki Hazama, Masato Saito, H. Meguro, Ken Conley, Khandker N. Quader, J.J. Chen · IEEE Journal of Solid-State Circuits · 2002
A single 3-V only, 1-Gb NAND flash memory has been successfully developed. The chip has been fabricated using 0.13-/spl mu/m CMOS STI technology. The effective cell size including the select transistors is 0.077 /spl mu/m/sup 2/. To decrease the chip size, a new architecture is introduced. The in-series connected memory cells are increased from 16 to 32. Furthermore, as many as 16 k memory cells are connected to the same wordline. As a result, the chip size is decreased by 15%. A very small die size of 125 mm/sup 2/ and an excellent cell area efficiency of 70% are achieved. As for the performance, a very fast programming and serial read are realized. The highest program throughput ever of 10.6-MByte/s is realized: 1) by quadrupling the page size and 2) by newly introducing a write cache. In addition, the garbage collection is accelerated to 9.4-MByte/s. In addition, the write cache accelerates the serial read operation and a very fast 20-MByte/s read throughput is realized.