Innovative System-level Design Environment Based on FORM for Transport Processing System
Kazushige Higuchi, Kazuhiro Shirakawa · 2008
This paper presents a system-level design environment for data transport processing systems. In this environment, designers can easily verify system behavior by formally defining data structures and their related actions, without considering detailed timing. In addition, the verified specification can be translated into synthesizable RTL descriptions by a dedicated RTL generator. Thus, using lower-level EDA tools, actual hardware can be obtained directly from a system-level specification.