Supporting quality of service in a terabit switch
K. James, K.Y. Yun · 2002
We discuss a novel architecture for performing very high speed cell switching with earliest-deadline-first scheduling. An input queued switch with central EDF contention resolution is presented. Static RAM buffers are used in conjunction with fast hardware queues that sort ensembles of equivalent cells. Simulation results show that this approach yields low latency in the presence of bursty traffic, without requiring large queues to prevent cell loss. The results compare favorably to those of an ideal output buffered switch that could not be implemented at a similar link rate and cost.