VLSI architectures for median filtering with linear complexity
Erl‐Huei Lu, Jau‐Yien Lee, Yawpo Yang · 2002
Two hardware architectures for median filtering with linear complexity are presented. Both of them are very suitable to implement a filter of large window size owing to their linear hardware complexity. Also, they are suitable for high-speed signal processing because each of them can generate one filtered word in a system clock.