A Novel VLSI Architecture for VBSME in MPEG-4 AVC/H.264
Wei Cao, Mao Zhi Gang · 2005
Variable block-size motion estimation (VBSME) is adopted in the MPEG-4 AVC/H.264 standard. In this paper, we proposed a new reconfigurable VLSI architecture for VBSME with FBMA to support a "meander"-like scan format for a high data reuse of the search area. The architecture can reuse the smaller blocks' sum of absolute differences to calculate 41 motion vectors (MVs) of a 16/spl times/16 block in parallel. Our design was implemented with 0.25 /spl mu/m CMOS technology. Under a clock frequency of 52 MHz, the architecture allows the real-time processing of 720/spl times/576 at 30 fps in a search range [-6, +15].