A triple-mode LDPC decoder design for IEEE 802.11n SYSTEM
Min-An Chao, Jen-Yang Wen, Xin-Yu Shih, An-Yeu Andy Wu · 2009
This paper shows a triple-mode LDPC decoder design with two design techniques, the matrix reordering algorithm for multi-mode reconfiguration and the single-entry-multiple-data (SEMD) scheme for throughput enhancement. The matrix reordering algorithm can reduce the computational complexity from O(n!) to O(n3). The SEMD can enhance the throughput by m times with small area overhead. With TSMC 0.13 mum CMOS, the proposed design is synthesized in 1.99 mm2area at 172.4 MHz.