Methodology and code reuse in the verification of telecommunication SOCs
O.A. Petlin, A. Genusov, L. Wakeman · 2002
Rapid developments in semiconductor technologies have opened a broad spectrum of opportunities for the telecommunication industry to produce complex systems from a number of predesigned cores on a single chip. System-on-Chip (SOC) designs bring new verification challenges that become critical issues under the 'time-to-market' pressure. The reuse of verification code and methodology is a major factor providing significant reduction of the overall verification costs. A high-level description of the C-based verification system used for the verification and co-simulation of telecommunication SOCs is described in this paper. The verification core is based on the TestBenchPlus (TBP) software developed by ASIC Alliance Corp. The C language abstraction level, combined with a set of predesigned low-level C and VHDL routines, creates powerful verification framework. The proposed verification methodology has proven to be reusable across a number of projects with the leading producers of telecommunication SOCs. The verification system reusability is provided by a flexible user interface, environment structure, testbench design and verification methodology.