A 80 MFLOPS 64-bit microprocessor for parallel computer
Hiraku Nakano, M. Nakajima, Yasuhiro Nakakura, T. Yoshida, Yoshiyuki Goi, Yuji Nakai, Reiji Segawa, Takeshi Kishida, H. Kadota · 2002
A 80-MFLOPS 64-bit microprocessor is described that employs superscalar architecture to execute two instructions, including the combination of 64-bit floating-point add and multiply instructions, in one 25-ns cycle simultaneously. The processor, implemented in a 0.8- mu m CMOS technology, contains 1300 K transistors. The processor also employs a RISC (reduced instruction set computer) architecture and Harvard-style bus organization. Division is accomplished every 200 ns. A typical performance is 64 MFLOPS.>