Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms
Dimitri Kagaris, Spyros Tragoudas, Dimitrios Karayiannis · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1997
Nonenumerative path-delay fault coverage estimation for combinational circuits estimates the fault coverage of a given test set without explicit enumeration of all paths in the circuit. In a recent nonenumerative method, it was proposed that a set C of lines be located in the circuit so that the set forms a cut and no lines in the set belong to the same path. Each line in the cut defines a subcircuit consisting of all paths that contain the line. Fault coverage may be obtained by working on all the subcircuits without double-counting path-delay faults. The main result of this paper is a polynomial time algorithm for finding a maximum cardinality set C. Besides its theoretical importance, our extensive experimental results on the ISCAS'85 benchmarks show that the larger the set C (and the number of subcircuits), the better the fault coverage estimation. More subcircuits may be generated only in a heuristic manner. It was proposed to consider two or more line-disjoint cuts C/sub i/. We propose a technique where only one C/sub i/ must be a cut. This scheme is based on novel algorithms and results in more subcircuits than the previous one.