A pipelined shared-memory architecture for FFT processors
Lihong Jia, Yonghong Gao, Hannu Tenhunen · 2003
This paper presented a VLSI-architecture for the FFT processors-which locally employed the pipelined architecture to realize the high speed radix-r Process Elements (PEs) and globally utilized the high-radix shared-memory architecture to implement the area-efficient FFT processors. Based on this architecture, a high performance 512-point FFT processor has been designed in the 0.6 um 3.3 v CMOS process to demonstrated its feasibility.