Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
Francisco Barat, Murali Jayapala, Pieter Op De Beeck, Geert Deconinck · 2002
This paper shows that software pipelining can be an effective technique for code generation for coarsegrained reconfigurable instruction set processors. The paper describes a technique based on software pipelining that performs reconfigurable instruction generation and instruction scheduling on a combined algorithm. Although typical compiler for reconfigurable processors perform these steps separately, results shows that the combination allows a successful usage of the reconfigurable resources. The technique presented is also able to exploit spatial computation inside the reconfigurable functional unit by which the output of a processing element is directly connected to the input of another processing element without the need of an intermediate register. Results show that it is possible to reduce the cycle count by using spatial computation. 1