64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency
R. Heald, Keun Wook Shin, V. Reddy, I-Feng Kao, M. Khan, William L. Lynch, Gary Lauterbach, Joseph Petolino · IEEE Journal of Solid-State Circuits · 1998
Address base-plus-offset summing is merged into the decode structure of this 64-KByte (512-Kbit), four-way set-associative cache. This address adder avoids time-consuming carry propagation by using an A+B=K equality test. The combined add and access operations are implemented using delayed-reset logic and a 0.25-/spl mu/m process, This wave pipelined RAM achieves a 1.6-ns cycle time and 2.6-ns latency for the combined address add and cache access.