Data routing: a paradigm for efficient data-path synthesis and code generation
Dirk Lanneer, Marco Cornero, Gert Goossens, Hillarie Man · 1994
Describes a new and effective approach to register and interconnect optimisation, which is applicable in a dual context: to reduce chip area in high-level synthesis, and to reduce resource load (and thus execution time) in retargetable code generation. The key idea is to carefully optimise the way in which data is transferred between functional units. The impact on high-level synthesis is demonstrated with a practical design from the area of telecommunications. >