A highly integrated GPS receiver for cellular handset
Francesco Dantoni, A. Holden, Song Fu, D. Sahu, Srinivasan Venkatraman, Sherif H. K. Embabi · 2002
A highly integrated dual conversion heterodyne GPS receiver is reported. The receiver chip includes a 2.9 dB NF LNA, an image-reject mixer with 32 dB image rejection. The on-chip IF chain, which consists of a VGA, a 2nd mixer and filtering, has a maximum gain of 83 dB, a gain range of 45 dB and a 7 dB NF. A 4-bit ADC is integrated on chip for enhanced SNR. The PLL with its VCO are also integrated. The total NF is 3 dB with a total 121 dB voltage gain. The chip consumes 132 mW at 2.7 V.