A computer architecture for the dynamic optimization of high-level language programs
Samuel P. Harbison · 1980
One of the disadvantages of high-level languages has been the necessity of using expensive optimizing compilers to generate efficient object code. This thesis describes and analyzes TM, a computer architecture that dynamically performs many optimizations commonly seen in such compilers, including common subexpression elimination, code motion, and register allocation. The architecture is based on an efficient, stack-oriented instruction set and is augmented with a special cache that holds the values of expressions and their dependencies. Experiments comparing the performance of TM and the a traditional register architecture on a set of test programs show that a simple, nonoptimizing compiler can generate object code for TM that is smaller and faster than the code produced by an optimizing compiler for the register architecture. A cost analysis shows that TM's hardware mechanisms need not be expensive in comparison with traditional architectures and that the savings in compiler development costs are significant. Additional experiments investigate cache behavior and analyze alternative implementations.