Pipelined architecture for fast CMOS buffer RAMs
Doris Schmitt‐Landsiedel, Brooke Hoppe, G. Neuendorf, Manfred Wurm, Josef Winnerl · IEEE Journal of Solid-State Circuits · 1990
A novel pipeline architecture for CMOS static RAMs (SRAMs) that allows operation at very high clock rates is described. Basic requirements for achieving high speed are the implementation of a hierarchical architecture and a memory cell with separate READ and WRITE data lines. The access speed of hierarchically organized memory blocks was between 2.5 and 3.5 ns. The maximum operating frequency of a 16 K pipelined hierarchical SRAM (PHSRAM) is in the range of 300 MHz. The hierarchical architecture and a seven-transistor memory cell provide a circuit using digital swings all over. Key advantages of the full-swing static logic circuitry are robustness with respect to fabrication tolerances and a high-noise immunity. Moreover, the circuit can be reduced to finer structure sizes without any redesign, since there are no critical analog circuit parts.>