Partial scan testing with single clock control
Vishwani D. Agrawal, T.J. Charkraborty · 2002
Gives methods of test generation for partial scan circuits in which a single system clock controls all flip-flops in both functional and scan modes. Scan flip-flops are selected to break cycles. In comparison to circuits with separate scan clock, the single clock tests can cover most detectable faults with shorter test sequence. However, test generation time is increased.>