Analysis of bit transition count for EDAC encoded FSM
N. Venkateswaran, V. Balaji, Venkataraman Mahalingam, T.L. Rajaprabhu · 2004
The focus of this paper is to present a bit transition count analysis for various error detection and correction (EDAC) schemes through a detailed simulation. The simulation also brings out the impact of various EDAC schemes - linear, BCH, m-out-of-n, Berger and SEC-MUED - on bit transition count with respect to number of FSM partitions under different partitioning objective functions for low power. A decrease up to 30 percent in bit transitions count under the three partitioning objectives has been observed.