Synfinity II-a high-speed interconnect with 2 GBytes/sec self-configurable physical link
Yoichi Koyanagi, T. Horie, T. Miyoshi, M. Ishii · 2002
We developed a high-speed low-latency interconnect chipset, Synfinity II. It is aimed to provide a common interconnect infrastructure which is applicable to connect microprocessors, memories, I/O devices and storage/network subsystems. To build a high-performance system, not only high bandwidth but also low latency is required for the interconnect. Moreover RAS (reliability, availability, serviceability) features are key attributes for high quality data communication. Synfinity II interconnect is designed to achieve following goals: high-bandwidth and low-latency data transfer, scalable and flexible architecture, RAS features, and cost effectiveness. This paper describes how we achieved these goals in Synfinity II. Details of the 2 GBytes/sec/direction physical link, the interface chip, MIC2, and the six-port switch chip, Router2, are also explained. The switch chip Router2 provides 24 Gbytes/sec aggregate bandwidth. These chips performed stable data transfer and the RAS functions were confirmed in the workstation cluster system.