Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain
Tom Waayers, Richard Morren, R. Grandi · 2006
This paper presents a new modular SOC test architecture that uses an improved single TAM daisy-chain for scan test access to embedded modules. The architecture by definition guarantees that the total SOC test time is close to the lower bound. To make third party IP cores to fit the architecture, IP with test infrastructure 'on-demand' is introduced. An area-efficient bypass implementation for our IEEE std. 1500 compliant test wrapper is presented and results from a single TAM daisy-chain on silicon are shown.