Micropipeline architecture for multiplier-less FIR filters
Saeid Nooshabadi, Juan Antonio Montiel-Nelson, G. S. Visweswaran, D. Nagchoudhurhi · 2002
In this paper asynchronous design techniques are employed to implement a multiplierless FIR filter. Suitability of modular, micropipelined based design style for mapping of the DSP algorithms into VLSI hardware has been demonstrated. In this design global clock has been eliminated, thereby, reducing the complexity associated with the clock distribution network.