Design and Implementation of a 64/32-bit Floating-point Division, Reciprocal, Square root, and Inverse Square root Unit
Chen Shuang-yan, Donghui Wang, Tiejun Zhang, Hou Chao-huan · 2006
This paper presents an efficient design and implementation of a configurable multifunctional floating-point unit for the computation of division, reciprocal, square root and inverse square root, which is fully compatible with the IEEE754 standard. Based on the Newton-Raphson method and utilizing fast parallel multipliers, the design is fast, scalable, easy to pipeline, and has very high precision. The design is implemented in Verilog, simulated in ModelSim, and then synthesized using synopsys design compiler with SMIC 0.18 micron standard cell library. Under worst condition, the critical path delay is 4.55ns