DFT architecture for a dynamic fault model of the embedded mask ROM of SOC
Yang-Han Lee, Yih-Guang Jan, Jei-Jung Shen, Shian-Wei Tzeng, Ming‐Hsueh Chuang, Jheng-Yao Lin · 2005
This paper describes a fail situation in the mass product testing of the embedded NAND-type mask ROM of a SOC "of passing in the high speed test, but fails in the low speed test", and propose a fault model of the situation. We also propose a general solution of testing to cope with this fault model. Finally, we invent DFT architecture to cover the fault model to reduce the testing time.