A single-chip FPGA implementation of the data encryption standard (DES) algorithm
Kenneth Koon‐Ho Wong, M. Wark, Ed Dawson · 2002
This paper describes a single-chip implementation of the data encryption standard (DES) using Xilinx XC4000 series field programmable gate array technology under the XACTstep design flow integration system. The implementation details for key scheduling, S-boxes, permutations and the round-function are described. The design process included schematic design, functional and timing simulation and design verification. The final design used 224 combinational logic blocks (CLBs) and 54 input/output blocks (IOBs) and has an encryption speed of 26.7 Mbps.