Implementation of Multiplier Block with Reduced Adder Cost
Somayyeh Rahimian Omam, Mohamadreza Mortazavi, Seid Mehdi Fakhraie, O. Shoaei · 2006
The hardware complexity of digital filters (and many other DSP modules) is mainly dominated by the coefficient multipliers. Implementing fixed-point coefficient multiplication as a network of adders, subtractors and shifters, yields lower power consumption. In such filters the number of adders (and subtractors) determines the implementation cost. The reason is that shifts are implemented as hard-wired inter-block connections and are considered "free". In transposed implementation of an FIR filter, each input is multiplied by several coefficients. Considering all coefficients as a multiplier block and omitting the redundancies by sharing the common fundamentals among different coefficients, yields great reduction in the number of arithmetic operations. This paper presents a graph based algorithm to reduce the computational complexity of multiple constant multiplications. Simulation results show that using the proposed method results good improvement in adder cost of multiplier blocks.