Area efficient synthesis of asynchronous interface circuits
Ruchir Puri, Jinlong Gu · 2002
Asynchronous circuits are widely used in many real time applications such as digital communication and computer systems. The design of complex asynchronous interface circuits is a difficult and error-prone task. We present an area and time efficient synthesis algorithm for general signal transition graph (STG) specifications. It utilizes a divide-and-conquer approach to significantly reduce the number of design constraints. We present a BDD constraint satisfaction algorithm that exploits the don't cares for area efficient synthesis. Experimental results with a large number of practical signal transition graph benchmarks are presented. These results show that compared to the existing techniques, the divide-and-conquer BDD technique is capable of achieving an average of 20% reduction in implementation area.>